Metal-oxide-semiconductor field effect transistors (MOSFETS) are well known and widely used in the electronics industry. MOSFETs are generally fabricated by diffusing two, spaced n-type regions (known as the source and drain) into a p-type substrate or by diffusing two, spaced p-type regions into an n-type substrate, producing an n-channel MOSFET or a p-channel MOSFET respectively. Additionally, a metal gate electrode is disposed over the substrate region separating the source and drain and is insulated therefrom by a layer of insulating material such as an oxide (gate oxide). For an n-channel metal-oxide semiconductor (NMOS) device, when a positive voltage is applied to the gate, the field from the gate will draw electrons into the substrate region surrounding the gate causing a channel to be formed between the drain and the source. This formed or induced channel allows current to flow between the source and drain electrodes of the transistor.
Market forces are requiring an increasing number of transistors to be situated on an integrated circuit (IC) chip without increasing the overall size of the IC chip. These demands for miniaturization of integrated circuits have resulted in the requirement for thinner gate oxide layers (e.g., about on the order of &lt;40 .ANG., which is only several atomic layers thick). The thickness of gate oxides is made as small as possible because the drive current in MOSFETs increases with decreasing gate oxide thickness. Furthermore, thin oxides (and shallow junction depths) are desired to control short channel effects (e.g., thin gate oxides permit the gate to retain strong control of channel charge, and shallow junctions keep the drain field from extending far into the channel). However, it is very difficult to control uniform growth of gate oxides of such small thickness. As is known, the thickness of the gate oxide needs to be well characterized in order to maintain consistency and reliability in performance of the MOSFET device. Moreover, small defects or contamination in the thin gate oxide may lead to inoperabilty of the MOSFET device. In order to overcome such design constraints, materials of higher dielectric constant (e.g., .epsilon.&gt;100) are being employed as the gate oxide material. The benefit of employing a higher dielectric constant material is that doing so permits use of a thicker gate oxide while retaining most of the benefits of a thinner gate oxide (e.g., comprising SiO.sub.2) thus avoiding the aforementioned problems of controlling uniform growth of a very thin gate oxide and/or device inoperability due to minor defects or contamination. More particularly, instead of using 40 .ANG. of a low dielectric constant gate oxide material (e.g., SiO.sub.2), 500 .ANG. of a high dielectric gate oxide material may be used instead. Controlled uniform growth of about 500 .ANG. thick gate oxide is substantially easier than controlled uniform growth of a gate oxide of about 40 .ANG. thickness.
However, the inventors of the present invention have found that employment of such high dielectric constant materials for the gate oxide result in enhanced gate fringing (GF) fields in the device to a point where gate capacitance is lowered so much that the device becomes unreliable. Gate capacitance affords for turning "ON" and "OFF" the MOSFET. Because the gate capacitance is significantly lowered by the enhanced GF fields, gate current leakage results making the device substantially impossible to turn off. Thus, the conventional employment of high dielectric material in formation of a gate oxide may lead to device inoperabilty due to the enhanced GF fields.
Consequently, there is a need in the art for a method of fabricating a reliable MOSFET device which avoids the design constraints associated with growing uniform very thin gate oxides and also mitigates the enhanced GF field effects associated with using gate oxide materials of high dielectric constant.